This is the target cell for a lower-cost, self-integrated space solar panel: a 40 × 40 mm square silicon heterojunction cell packaged as a covered, interconnected cell. The square outline is intentionally ordinary. It can be cut from a conventional wafer with little geometric waste, tiled in rows without handed parts, and inspected with straightforward machine vision.
The interactive model separates the package into its functional layers. Use the explosion control to open the stack, select a layer to isolate it, or click directly on the model to inspect its purpose, thickness, and proposed material.
Assembly recipe
Each row is a physical component and each column is a manufacturing step. A vertical span means that every component row covered by the cell is combined during that step. The widening spans make the nested assembly sequence visible: two components become the optical cover, two become the contacted cell, three become the protected cell, five become the CIC, and all seven become the panel-ready cell.
| Component | Prepare | Contact | Protect | Package CIC | Mount |
|---|---|---|---|---|---|
| Coverglass | Clean surfaces Apply optical adhesive ↓ Prepared optical cover |
Hold | Hold | Align optical cover with protected cell Bond and cure ↓ Covered interconnected cell |
Position CIC on mounting interface Bond and connect into string ↓ Panel-ready square cell |
| Optical adhesive | Hold | Hold | |||
| HJT silicon cell | Clean and inspect | Attach interconnects to cell contacts ↓ Contacted cell |
Connect bypass diode across contacted cell ↓ Protected, stringable cell |
||
| Front and rear interconnects | Form and clean | ||||
| Bypass diode | Orient and inspect | Place at cell contacts | |||
| Laydown adhesive | Prepare dielectric and apply adhesive ↓ Insulated mounting interface |
Hold | Hold | Hold completed CIC | |
| Kapton dielectric | Hold | Hold | Hold completed CIC |
Target specification
| Property | Target |
|---|---|
| Cell outline | 40 × 40 mm square |
| Active area | approximately 15.2 cm² |
| Silicon wafer | 100 µm n-type monocrystalline silicon |
| Cell architecture | silicon heterojunction, bifacial-capable |
| Target AM0 BOL efficiency | 23–25% |
| Target AM0 BOL power | 0.47–0.51 W |
| Coverglass | 100 µm CMG/CMX-type ceria-doped microsheet |
| Cell-level bypass protection | one discrete silicon diode |
| Estimated CIC thickness | approximately 0.28–0.34 mm |
| Estimated CIC mass | approximately 0.9–1.1 g |
The power estimate uses the standard AM0 irradiance of 135.3 mW/cm² and reserves roughly five percent of the square for edge clearance, contacts, and the diode corner.
Exploded stack
From the Sun-facing surface downward, the target stack is:
- Ceria-doped coverglass rejects damaging ultraviolet radiation and slows radiation-induced output loss.
- Optically clear silicone bonds the glass without imposing a rigid thermal-expansion constraint on the silicon.
- Front transparent conductor and silver grid collect current while leaving most of the surface illuminated.
- Intrinsic and doped amorphous-silicon films passivate the crystalline wafer and form the front heterojunction.
- The crystalline-silicon absorber supplies nearly all of the device thickness.
- Rear amorphous-silicon and transparent-conductor films form the back junction and rear electrical contact.
- Rear metallization and interconnect pads connect the cell into a series string.
- A discrete bypass diode conducts around a shaded or damaged cell before reverse bias destroys it.
- Low-outgassing laydown silicone attaches the CIC to the panel while absorbing differential expansion.
- Kapton HN dielectric film separates the live cell circuit from the conductive panel facesheet.
Nanometre-scale semiconductor films and micrometre-scale metal layers would disappear at true scale. The model therefore maps physical thickness to a readable visual thickness while displaying the real target dimension in the inspector.
Why HJT silicon
Heterojunction cells combine a crystalline silicon absorber with very thin amorphous-silicon passivation layers. The architecture is attractive for this experiment because it can use mature terrestrial wafer and coating equipment, operates with a relatively low temperature coefficient, and can be made on wafers substantially thinner than common terrestrial modules.
The economic target is not to outperform ZTJ by area. It is to deliver substantially more watt-years per dollar in LEO when the spacecraft can accept roughly 30–40% more illuminated area. Radiation-resistant coverglass remains the largest non-silicon material cost, so the design treats the coverglass and its bond as first-class components rather than terrestrial encapsulation.
Assembly boundary
The model stops at the Kapton interface. The carbon-composite facesheet, aluminum honeycomb core, string blocking diode, harness, connector, and rear thermal-control coating belong to the panel rather than the replaceable cell package.
This is a reverse-engineered design target, not a qualification claim. A flight version still needs measured AM0 performance, coverglass transmission data, thermal-vacuum cycling, interconnect fatigue testing, radiation exposure, insulation testing, and lot-level material traceability.