1. The foundation built on redundancy

Isaac Asimov’s Foundation returns as the recalled work because Hari Seldon’s plan does not rely on any single institution, person, or prediction. It survives because it is distributed and redundant: if one branch of the encyclopedia project fails, the others carry the knowledge forward. Spacecraft computing works the same way.

This entry reads about fault-tolerant computing techniques.

2. Error detection and correction

The first line of defense is error detection and correction (EDAC), usually implemented with Hamming or similar codes in memory and sometimes in buses:

  • Parity detects a single-bit error but cannot correct it.
  • Single-error-correct, double-error-detect (SEC-DED) codes can fix one bit flip and flag two.
  • More advanced codes can correct multi-bit errors at the cost of more redundancy and latency.

EDAC is cheap and effective against SEUs. Its limitation is that it protects data at rest or in transit, not necessarily the logic that operates on the data.

3. Triple modular redundancy

Triple modular redundancy (TMR) runs three copies of the same logic or computation and votes on the output. If one copy disagrees, the majority wins. A NASA S3VI student paper on fault-tolerant computer architecture describes TMR as a classic approach for critical computational hardware.

TMR protects against transient faults in logic as well as memory, but it costs roughly three times the hardware, power, and area. It is also vulnerable to common-mode failures if all three copies are hit by the same event or share the same design flaw.

4. Scrubbing

For FPGAs and memory, scrubbing periodically reads the configuration or data, corrects any detected errors, and writes it back before errors accumulate. A Pitt Space report on hybrid and reconfigurable fault tolerance identifies scrubbing as essential for SRAM-based FPGAs, whose configuration bits are themselves sensitive to SEUs.

Without scrubbing, an FPGA might operate perfectly while its underlying configuration silently accumulates bit flips until the fabric implements something other than the intended design.

5. Watchdogs and current limiting

At the system level, watchdog timers detect when a processor has stopped behaving correctly and force a reset. Current-limiting power switches detect latchup events and remove power before thermal runaway destroys the part. These are simple, fast, and mechanical in spirit: if the current is wrong, turn it off.

6. Software fault tolerance

Software complements hardware. Techniques include:

  • Assertion and sanity checks: detect impossible or inconsistent states.
  • Checkpoint and rollback: restart a computation from a known good point.
  • Diverse implementation: run the same critical function two different ways and compare results.
  • Graceful degradation: reduce functionality rather than fail entirely.

An NSF SHREC paper on hybrid computing for small satellites notes that fault tolerance always trades hardware, software, performance, and cost.

7. What this changes

  • No single technique is enough; layered defense is standard practice.
  • EDAC for memory, TMR for critical logic, scrubbing for FPGAs, and watchdogs/current limits for catastrophic events form a coherent stack.
  • The desktop can combine COTS compute with these techniques rather than relying solely on rad-hard parts.
  • The next entry will synthesize the radiation reading arc into requirements for the desktop.