1. The monks of data

Walter M. Miller Jr.’s A Canticle for Leibowitz is about monks who preserve fragments of technical knowledge across centuries of collapse. Their problem is not just keeping the books safe; it is keeping the books readable, copied, and understood as languages and technologies change. Storage in orbit has the same shape: the bits must survive not only the medium but also the environment that slowly degrades it.

This entry reads about how COTS storage and memory devices behave under LEO radiation.

2. Memory technologies and their radiation sensitivities

The desktop’s storage story is likely a stack of technologies, each with its own vulnerabilities:

  • SRAM: fast and simple, but the smallest memory cell is also the easiest to upset. A single ion can flip a bit. SRAM-based FPGAs share the same problem: their configuration memory is essentially SRAM, so an SEU can rewire the device.
  • DRAM: stores charge in a capacitor. It is denser and generally less SEU-sensitive per bit than SRAM, but it requires refresh cycles, and radiation can accelerate leakage or corrupt refresh logic.
  • NAND flash: stores charge on a floating gate. It is non-volatile and dense, but the control circuitry — charge pumps, state machines, output buffers — is often more radiation-sensitive than the memory array itself. TID can shift threshold voltages and reduce program/erase margins.
  • EEPROM: similar floating-gate physics to flash, with similar vulnerabilities in the peripheral circuitry.

The Padua thesis on flash memory notes that the control circuitry is usually the weakest part of a commercial device. The floating-gate array can survive substantial TID, but if the charge pump or state machine fails, the whole device becomes unusable.

3. Error correction as the practical shield

For LEO missions, radiation-tolerant storage is usually achieved through error correction and redundancy rather than radiation-hardened silicon. The ATP overview describes the standard stack:

  • SECDED (single-error-correct, double-error-detect) at the SRAM/DRAM level.
  • LDPC (low-density parity-check) and read-retry at the NAND flash level.
  • End-to-end data path protection from host to controller to NAND.
  • RAID-like parity across multiple flash dies or devices.
  • Scrubbing: periodic reads with correction to prevent bit errors from accumulating beyond the correction threshold.

This approach accepts that bits will flip and that the system must detect and correct them faster than they can accumulate into uncorrectable errors.

4. Synergistic effects

The CORE paper on synergism between SEE and TID notes that the two effects are not independent. As TID accumulates, the SEU cross-section of some SRAM devices increases. A device that passes an SEU test at low dose may become more upset-prone after it has absorbed mission dose. This matters for long-duration missions: a part that looks fine at launch may degrade into a higher-error-rate part over time.

5. What this changes

  • The desktop’s storage strategy should assume bit errors will happen and budget for correction.
  • The most vulnerable part of a flash device is often the controller, not the memory array.
  • A storage cell that only reports raw bit error rate without correction margin is not telling the whole story.
  • The next entry will synthesize what the radiation literature means for the desktop as a whole.